1. Field of the Invention
This invention relates to integrated circuit structures with reduced capacitance. More particularly, this invention relates to the formation of an integrated circuit structure with low dielectric constant dielectric material formed between horizontally closely spaced apart metal lines of an integrated circuit structure to reduce horizontal capacitance between closely spaced apart metal lines, while via poisoning in vias formed through dielectric material down to the metal lines is mitigated due to the presence of silicon oxynitride caps on the metal lines.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled xe2x80x9cPursuing the Perfect Low-K Dielectricxe2x80x9d, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH3xe2x80x94SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400 C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Trikon process.
The use of this type of low k material has been found to result in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the horizontal capacitance between such adjacent metal lines on the same metal wiring level.
However, the substitution of such low k dielectric materials for conventional silicon oxide insulation has not been without its own problem. It has been found that the subsequent formation of vias, or contact openings, through such low k dielectric material to the underlying conductive portions (such as metal lines, or contacts on an active device), can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces, resulting in unfilled vias. Apparently the presence of carbon in the low k dielectric material formed by the Trikon process renders the material more susceptible to damage during subsequent processing of the structure. For example, contact openings or vias are usually etched in the dielectric layer through a resist mask. When the resist mask is subsequently removed by an ashing process, damage can occur to the newly formed via surfaces of the low k material resulting in such via poisoning.
Copending U.S. patent application Ser. No. 09/426,061 entitled xe2x80x9cLOW DIELECTRIC CONSTANT SILICON OXIDE-BASED DIELECTRIC LAYER FOR INTEGRATED CIRCUIT STRUCTURES HAVING IMPROVED COMPATIBILITY WITH VIA FILLER MATERIALS, AND METHOD OF MAKING SAMExe2x80x9d, was filed by one of us with others on Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of Ser. No. 09/426,061 is hereby incorporated by reference. In one embodiment in that application, low k silicon oxide dielectric material having a high carbon doping level is formed in the high aspect ratio regions between closely spaced apart metal lines and then a second layer comprising a low k silicon oxide dielectric material having a lower carbon content is then deposited over the first layer and the metal lines.
Copending U.S. patent application Ser. No. 09/426,056 entitled xe2x80x9cLOW K DIELECTRIC COMPOSITE LAYER FOR INTEGRATED CIRCUIT STRUCTURE WHICH PROVIDES VOID-FREE LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE MITIGATING VIA POISONINGxe2x80x9d, was filed by one of us with others on Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of Ser. No. 09/426,056 is also hereby incorporated by reference. In one embodiment in that application, a void-free low k silicon oxide dielectric material is formed in the high aspect regions between closely spaced apart metal lines by one of several processes, including the process used to form the first low k silicon oxide dielectric material described in the previously cited Ser. No. 09/426,061 patent application. A second layer of low k silicon oxide dielectric material is then deposited over the first layer and the metal lines by a process which deposits at a rate higher than the deposition rate of the void-free dielectric material. In a preferred embodiment, both of the layers are formed in the same vacuum chamber without an intervening planarization step.
Thus, it is highly desirable to provide a structure having a low k dielectric layer, and a process for making same, wherein a dielectric layer is formed comprising low k silicon oxide dielectric material with void-free filling characteristics for high aspect ratio regions between closely spaced apart metal lines while mitigating the poisoning of vias subsequently formed in the dielectric layer down to the metal lines.
In accordance with the invention, a capping layer of silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k dielectric material is then formed over the planarized void-free low k dielectric layer and the silicon oxynitride caps. Vias are then formed through the further dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.